You Shall Not Stall: Achieving RISC-V On-Demand Runtime-Reconfiguration using SCAIE-V

Embedded computing platforms increasingly require adaptable architectures to meet varying application demands. This paper explores how the instruction set of RISC-V-based microcontrollers can be extended at runtime using reconfigurable hardware accelerators and the SCAIE-V framework. Building on a flexible infrastructure based on dynamic partial reconfiguration and a scalable, standardized instruction interface within the pipeline, we demonstrate the integration of application-specific accelerators without sacrificing general-purpose capabilities. The experimental proof of concept based on the ASCON lightweight cryptographic algorithm validates the approach across two soft microcontrollers. With this, we showcase the usage of a software fallback mechanism to support seamless hardware/software transitions and enable memory handover between the software and hardware execution domains. The results show clear advantages in execution time and flexibility over static hardware designs while supporting long-term maintainability and sustainability through hardware reuse.