Random Delay Generator for Stochastic On-Chip Calibration of Sub-20 ps Custom CMOS TDCs

We propose a CMOS random delay generator circuit for stochastic calibration of Time to Digital Converters (TDC) with picosecond resolution. This method, known from FPGA-based TDC systems, determines the average bin width based on numerous measurement events of time intervals with a uniform probability distribution. We demonstrate the requirements for the random number generator sub-block, in terms of circuit parameters, to achieve the desired uniform distribution. Further, we show the importance of linearity in the Delay Generator transfer function for passing the uniformity goodness tests. The designed random delay generator is suitable for CMOS onchip integration together with TDC converter, to enable continuous monitoring of the resolution along the lifetime.