Impact of Random Telegraph Noise on the Precision of a Sub 20 ps Cyclic Vernier Time-to-Digital Converter

As CMOS scaling results in more frequent statistical occurrence of dominant Random Telegraph Noise (RTN) in MOSFET transistors, we analyse the severity of this phenomenon on the precision of high-resolution on-chip time measurement. The analysis is focused on a cyclic Vernier Time-to-Digital Converter (TDC) designed in 28 nm bulk CMOS with 15 ps LSB. RTN occurrence at various amplitudes obtained experimentally is modeled in the TDC circuit simulations. It is observed that the severity of consequences can reach from 1–2 LSB to a much larger error of 20 LSB. Further, in this speed-, area- and power-efficient cyclic Vernier architecture, the possible RTN-induced measurement error shows a complex pattern across the measurement dynamic range. This work highlights reliability concerns of high-precision time measurements in scaled CMOS process nodes due to the increasing probability of occurrence of the discrete noise patterns.