A temperature analysis for NFC-powered smart lab-on-chip devices

Carolin Kollegger; Christoph Steffan; Philipp Greiner; Clemens Rabl; David Lugitsch; Gerald Holweg; Bernd Deutschmann

doi:10.1109/MWSCAS.2018.8623976

A temperature analysis for NFC-powered smart lab-on-chip devices

Carolin Kollegger
, Christoph Steffan
, Philipp Greiner
, Clemens Rabl
, David Lugitsch
, Gerald Holweg
, Bernd Deutschmann

Institute of Electronics (4390)

Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review

Abstract

This paper presents a temperature analysis for NFC-powered Lab-on-Chip (LoC) solutions. It is based on a monolithically implemented LoC and uses a 130 nm standard CMOS process. The LoC has an active chip area of 6.24 mm ² . An application-independent temperature gathering mesh is implemented on the chip substrate. It allows a real time NFC-caused temperature analysis. Measurement data regarding heat spreading, the influence of the glob top, and the effect of the PCB layout is presented. A warming reduction from 23.05°C to 3.8°C using the same power source is achieved. Detailed data on the temperature gradient over time for warming and cooling is also provided.

Original language	English
Title of host publication	2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Publisher	IEEE
Pages	1058-1061
Number of pages	4
Volume	2018-August
ISBN (Electronic)	9781538673928
DOIs	https://doi.org/10.1109/MWSCAS.2018.8623976
Publication status	Published - 22 Jan 2019
Event	61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada Duration: 5 Aug 2018 → 8 Aug 2018

Conference

Conference	61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Country/Territory	Canada
City	Windsor
Period	5/08/18 → 8/08/18

Keywords

130 nm
CMOS
Lab-on-chip
NFC

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/MWSCAS.2018.8623976

Cite this

Kollegger, C, Steffan, C, Greiner, P, Rabl, C, Lugitsch, D, Holweg, G & Deutschmann, B 2019, A temperature analysis for NFC-powered smart lab-on-chip devices. in 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018. vol. 2018-August, 8623976, IEEE, pp. 1058-1061, 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, Canada, 5/08/18. https://doi.org/10.1109/MWSCAS.2018.8623976

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title = "A temperature analysis for NFC-powered smart lab-on-chip devices",

abstract = " This paper presents a temperature analysis for NFC-powered Lab-on-Chip (LoC) solutions. It is based on a monolithically implemented LoC and uses a 130 nm standard CMOS process. The LoC has an active chip area of 6.24 mm 2 . An application-independent temperature gathering mesh is implemented on the chip substrate. It allows a real time NFC-caused temperature analysis. Measurement data regarding heat spreading, the influence of the glob top, and the effect of the PCB layout is presented. A warming reduction from 23.05°C to 3.8°C using the same power source is achieved. Detailed data on the temperature gradient over time for warming and cooling is also provided. ",

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author = "Carolin Kollegger and Christoph Steffan and Philipp Greiner and Clemens Rabl and David Lugitsch and Gerald Holweg and Bernd Deutschmann",

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doi = "10.1109/MWSCAS.2018.8623976",

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AU - Kollegger, Carolin

AU - Steffan, Christoph

AU - Greiner, Philipp

AU - Rabl, Clemens

AU - Lugitsch, David

AU - Holweg, Gerald

AU - Deutschmann, Bernd

PY - 2019/1/22

Y1 - 2019/1/22

N2 - This paper presents a temperature analysis for NFC-powered Lab-on-Chip (LoC) solutions. It is based on a monolithically implemented LoC and uses a 130 nm standard CMOS process. The LoC has an active chip area of 6.24 mm 2 . An application-independent temperature gathering mesh is implemented on the chip substrate. It allows a real time NFC-caused temperature analysis. Measurement data regarding heat spreading, the influence of the glob top, and the effect of the PCB layout is presented. A warming reduction from 23.05°C to 3.8°C using the same power source is achieved. Detailed data on the temperature gradient over time for warming and cooling is also provided.

AB - This paper presents a temperature analysis for NFC-powered Lab-on-Chip (LoC) solutions. It is based on a monolithically implemented LoC and uses a 130 nm standard CMOS process. The LoC has an active chip area of 6.24 mm 2 . An application-independent temperature gathering mesh is implemented on the chip substrate. It allows a real time NFC-caused temperature analysis. Measurement data regarding heat spreading, the influence of the glob top, and the effect of the PCB layout is presented. A warming reduction from 23.05°C to 3.8°C using the same power source is achieved. Detailed data on the temperature gradient over time for warming and cooling is also provided.

KW - 130 nm

KW - CMOS

KW - Lab-on-chip

KW - NFC

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BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018

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T2 - 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018

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ER -

A temperature analysis for NFC-powered smart lab-on-chip devices

Abstract

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this