Project Details
Description
When talking about IT-Security, resistance against attacks is the basis of Trust in ITSystems. The development of countermeasures against various attacks, such as SPA/DPA , SEMA/DEMA or DFA , has become a challenging topic for academia as well as industry over the last decade. Recent improvements in attack techniques (e.g. early propagation weakness in case of DPA) and findings about incompleteness of proposed countermeasures (e.g. MDPL ) have brought up new approaches towards attack resistance (improved MDPL for DPA, redundant calculation for DFA etc.). Unfortunately all those proposed countermeasures have in common, that they increase the power and energy consumption tremendously, and thus jeopardizing the intended usability for various applications, such as contactless operated ePassports or eID cards or battery powered mobile TPMs for use with m-commerce or eGovernment. This increase of power or energy consumption has basically two fundamental reasons, the first of which is the increase of switching activity, as it applies to randomization or masking techniques as well as to dual-rail pre-charge coding of signals e.g. in CMOS based technologies. The second effect being increased leakage current due to increased area consumption will become even more dramatically as production of security relevant circuitry shall move on to ever smaller deep submicron technologies, as e.g. expected in the field of smartcards, where 90 nm non-volatile memory (NVM) technologies are under development. As it is well understood leakage current can become a serious problem in such deep submicron technologies. Developers of attack countermeasures have been so much focussing on security only, that economical aspects have been more and more neglected recently. None of the lately proposed power-hungry hardware countermeasures has found its way into commercial products! There exists an urgent need for cooperative research to re-align the academic creativity with the industries needs. The POWER-TRUST project aims to achieve such re-alignment and to develop widely applicable countermeasures optimized in terms of power and energy consumption especially for upcoming new technologies and trustworthy security tokens in mass production.
| Status | Finished |
|---|---|
| Effective start/end date | 1/03/08 → 31/12/10 |
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A Continuous Fault Countermeasure for AES Providing a Constant Error Detection Rate
Medwed, M. & Schmidt, J.-M., 2010, 7th Workshop on Fault Diagnosis and Tolerance in Cryptography - FDTC 2010. IEEE-CS Press, p. 66-71Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review
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POWER-TRUST D3.4 Specification of hardware structures of test-chip 2
Kirschbaum, M., Szekely, A. & Tillich, S., 2010, .Research output: Book/Report › Commissioned report
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POWER-TRUST D4.1 Analysis Report of Test Chip 2 (IAIK)
Kirschbaum, M., Szekely, A. & Tillich, S., 2010, .Research output: Book/Report › Commissioned report