A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV

Robert Kappel; Mario Auer; Wolfgang Pribyl; Guenter Hofer; Gerald Holweg

A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV

Robert Kappel
, Mario Auer
, Wolfgang Pribyl
, Guenter Hofer
, Gerald Holweg

Institut für Elektronik (4390)

Publikation: Konferenzbeitrag › Paper › Begutachtung

Abstract

In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic’s switching threshold can be reduced by 89% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.

Originalsprache	englisch
Seiten	562-565
Seitenumfang	4
Publikationsstatus	Veröffentlicht - 2013
Veranstaltung	IEEE International Symposium on Circuits and Systems: ISCAS 2013 - Beijing, China Dauer: 19 Mai 2013 → 23 Mai 2013 http://ieee-cas.org/pubs/tcsvt/iscas-2013

Konferenz

Konferenz	IEEE International Symposium on Circuits and Systems
Land/Gebiet	China
Ort	Beijing
Zeitraum	19/05/13 → 23/05/13
Internetadresse	http://ieee-cas.org/pubs/tcsvt/iscas-2013

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title = "A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV",

abstract = "In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic{\textquoteright}s switching threshold can be reduced by 89\% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.",

author = "Robert Kappel and Mario Auer and Wolfgang Pribyl and Guenter Hofer and Gerald Holweg",

year = "2013",

language = "English",

pages = "562--565",

note = "IEEE International Symposium on Circuits and Systems : ISCAS 2013 ; Conference date: 19-05-2013 Through 23-05-2013",

url = "http://ieee-cas.org/pubs/tcsvt/iscas-2013",

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TY - CONF

T1 - A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV

AU - Kappel, Robert

AU - Auer, Mario

AU - Pribyl, Wolfgang

AU - Hofer, Guenter

AU - Holweg, Gerald

PY - 2013

Y1 - 2013

N2 - In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic’s switching threshold can be reduced by 89% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.

AB - In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic’s switching threshold can be reduced by 89% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.

M3 - Paper

SP - 562

EP - 565

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 19 May 2013 through 23 May 2013

ER -

A Process-Variation Compensation Scheme to Operate CMOS Digital Logic Cells in Deep Sub-Threshold Region at 80mV

Abstract

Konferenz

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