A Method for Fast Jitter Tolerance Analysis of High-Speed PLLs

Stefan Erb; Wolfgang Pribyl

doi:10.1109/DATE.2011.5763182

A Method for Fast Jitter Tolerance Analysis of High-Speed PLLs

Stefan Erb
, Wolfgang Pribyl

Institut für Elektronik (4390)

Publikation: Beitrag in Buch/Bericht/Konferenzband › Beitrag in einem Konferenzband › Begutachtung

Abstract

We propose a fast method for identifying the jitter tolerance curves of high-speed phase locked loops. The method is based on an adaptive recursion and uses known tail fitting meth-
ods to realize a fast optimization combined with a small number of jitter samples. It allows for efficient behavioral simulations, and can also be applied to hardware measurements. A typical
modeling example demonstrates applicability to both software and hardware scenarios and achieves simulated measurement times in the range of few hundred milliseconds.

Originalsprache	englisch
Titel	Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Herausgeber (Verlag)	IEEE
Seiten	1-6
ISBN (Print)	978-1-61284-208-0
DOIs	https://doi.org/10.1109/DATE.2011.5763182
Publikationsstatus	Veröffentlicht - 2011
Veranstaltung	Design, Automation and Test in Europe Conference and Exhibition: DATE 2015 - Grenoble, Frankreich Dauer: 10 März 2015 → 10 März 2015

Konferenz

Konferenz	Design, Automation and Test in Europe Conference and Exhibition
Land/Gebiet	Frankreich
Ort	Grenoble
Zeitraum	10/03/15 → 10/03/15

Fields of Expertise

Information, Communication & Computing

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10.1109/DATE.2011.5763182

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@inproceedings{e796a591a3184afb9d888c0cfbde95b8,

title = "A Method for Fast Jitter Tolerance Analysis of High-Speed PLLs",

abstract = "We propose a fast method for identifying the jitter tolerance curves of high-speed phase locked loops. The method is based on an adaptive recursion and uses known tail fitting meth- ods to realize a fast optimization combined with a small number of jitter samples. It allows for efficient behavioral simulations, and can also be applied to hardware measurements. A typical modeling example demonstrates applicability to both software and hardware scenarios and achieves simulated measurement times in the range of few hundred milliseconds.",

author = "Stefan Erb and Wolfgang Pribyl",

year = "2011",

doi = "10.1109/DATE.2011.5763182",

language = "English",

isbn = "978-1-61284-208-0",

pages = "1--6",

booktitle = "Design, Automation \& Test in Europe Conference \& Exhibition (DATE), 2011",

publisher = "IEEE",

address = "United States",

note = "Design, Automation and Test in Europe Conference and Exhibition : DATE 2015 ; Conference date: 10-03-2015 Through 10-03-2015",

}

TY - GEN

T1 - A Method for Fast Jitter Tolerance Analysis of High-Speed PLLs

AU - Erb, Stefan

AU - Pribyl, Wolfgang

PY - 2011

Y1 - 2011

N2 - We propose a fast method for identifying the jitter tolerance curves of high-speed phase locked loops. The method is based on an adaptive recursion and uses known tail fitting meth- ods to realize a fast optimization combined with a small number of jitter samples. It allows for efficient behavioral simulations, and can also be applied to hardware measurements. A typical modeling example demonstrates applicability to both software and hardware scenarios and achieves simulated measurement times in the range of few hundred milliseconds.

AB - We propose a fast method for identifying the jitter tolerance curves of high-speed phase locked loops. The method is based on an adaptive recursion and uses known tail fitting meth- ods to realize a fast optimization combined with a small number of jitter samples. It allows for efficient behavioral simulations, and can also be applied to hardware measurements. A typical modeling example demonstrates applicability to both software and hardware scenarios and achieves simulated measurement times in the range of few hundred milliseconds.

U2 - 10.1109/DATE.2011.5763182

DO - 10.1109/DATE.2011.5763182

M3 - Conference paper

SN - 978-1-61284-208-0

SP - 1

EP - 6

BT - Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011

PB - IEEE

T2 - Design, Automation and Test in Europe Conference and Exhibition

Y2 - 10 March 2015 through 10 March 2015

ER -

A Method for Fast Jitter Tolerance Analysis of High-Speed PLLs

Abstract

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